Raysen Industry Hong Kong Limited

技術問答

Technical Q&A

AI 數據中心電源管理與架構熱點技術問答

Key technical Q&A on AI data center power management and architecture

德州儀器2026年推出了哪些針對AI數據中心的新款電源管理芯片？ What new power management chips did Texas Instruments launch in 2026 for AI data centers?

TI推出了TPS1685（48V集成式熱插拔電子保險絲，帶電源路徑保護）和LMG3650R035/R025/R070（采用行業標準TOLL封裝的集成式GaN功率級系列）。TPS1685可支持6kW以上功率水平，GaN功率級實現>98%效率和>100W/in3功率密度。

TI introduced the TPS1685 (a 48V integrated hot-swap eFuse with power path protection) and the LMG3650R035/R025/R070 family (integrated GaN power stages in industry-standard TOLL packaging). The TPS1685 supports power levels above 6 kW, while the GaN power stages achieve >98% efficiency and >100 W/in3 power density.

TI與NVIDIA合作推出的800VDC電源架構的核心特點是什么？ What are the core characteristics of the 800 VDC power architecture co-developed by TI and NVIDIA?

該架構將800V到GPU核心電源的轉換路徑簡化為僅需兩級：先通過800V至6V隔離式母線轉換器（峰值效率97.6%，功率密度超2000W/in3），再通過6V至1V以下多相降壓方案。相比傳統架構大幅簡化了配電層級。

The architecture reduces the conversion path from 800V to GPU core voltage to just two stages: an 800V-to-6V isolated bus converter (97.6% peak efficiency, >2000 W/in3 power density), followed by a 6V-to-sub-1V multiphase step-down solution. This substantially simplifies the power distribution hierarchy compared with conventional architectures.

TI的800VDC架構包含哪些具體組件？ What specific components comprise TI's 800 VDC architecture?

包含800V熱插拔控制器、800V至6V DC/DC轉換器（集成GaN功率級）、6V至1V以下多相降壓轉換器、30kW 800V高功率密度AC/DC PSU，以及采用EDLC超級電容器單元的800V電容器組（功率密度40W/in3）。

It includes an 800V hot-swap controller, an 800V-to-6V DC/DC converter with integrated GaN power stages, a 6V-to-sub-1V multiphase step-down converter, a 30 kW 800V high-power-density AC/DC PSU, and an 800V capacitor bank using EDLC supercapacitor cells (40 W/in3 power density).

TPS1685電子保險絲相比傳統熱插拔控制器有哪些改進？ How does the TPS1685 eFuse improve upon conventional hot-swap controllers?

TPS1685是48V可堆疊集成式熱插拔電子保險絲，具有電源路徑保護功能。相比市場上現有的熱插拔控制器，它簡化了設計并將解決方案尺寸縮小了一半，可擴展滿足>6kW的高功率處理需求。

The TPS1685 is a 48V stackable integrated hot-swap eFuse with power path protection. Compared with existing hot-swap controllers on the market, it simplifies design and halves solution size, while scaling to meet high-power handling requirements above 6 kW.

TI新款GaN功率級LMG3650系列的關鍵規格是什么？ What are the key specifications of TI's new LMG3650 GaN power stage family?

LMG3650R035/R025/R070集成高性能柵極驅動器與650V GaN FET，實現>98%效率和>100W/in3功率密度。集成保護功能包括過電流保護、短路保護和過溫保護，適用于伺服器電源等AC/DC應用。

The LMG3650R035/R025/R070 integrates a high-performance gate driver with a 650V GaN FET, achieving >98% efficiency and >100 W/in3 power density. Integrated protection features include overcurrent protection, short-circuit protection, and overtemperature protection, making it suitable for server power supplies and other AC/DC applications.

ADI的MAX20816多相控制器如何支持AI加速器供電？ How does ADI's MAX20816 multiphase controller support AI accelerator power delivery?

MAX20816基于雙環路靈活架構，支持最多16相可配置，分布在兩個獨立軌上。通過PWMVID和AVSBus數字接口實現快速精確的電壓控制，支持耦合電感和智能功率級，可擴展至32或48相，支持高達2500A電流。

The MAX20816 is built on a dual-loop flexible architecture supporting up to 16 configurable phases distributed across two independent rails. It achieves fast, precise voltage control through PWMVID and AVSBus digital interfaces, supports coupled inductors and smart power stages, and scales to 32 or 48 phases with current capability up to 2500A.

MAX20816在遙測和系統可靠性方面有哪些特性？ What telemetry and system reliability features does the MAX20816 offer?

集成PMBus遙測功能，可實時監測電壓、電流、輸入功率和功率級溫度。內置非易失性存儲器可存儲預設或自定義配置，故障記錄和保護功能有助于預防關鍵故障，特別適用于高功率密度環境。

It integrates PMBus telemetry for real-time monitoring of voltage, current, input power, and power-stage temperature. Built-in non-volatile memory stores preset or custom configurations, while fault logging and protection features help prevent critical failures, particularly in high-power-density environments.

ADI收購Empower Semiconductor的戰略目的是什么？ What is the strategic purpose behind ADI's acquisition of Empower Semiconductor?

ADI以15億美元收購Empower，旨在強化AI應用的高密度功率電子布局。Empower開發了集成電壓調節器（IVR）和硅基電容器技術，可實現更靠近處理器的功率轉換，縮短功率路徑、減少損耗。ADI CEO指出能源供應已成為AI系統擴展的首要瓶頸。

ADI acquired Empower for $1.5 billion to strengthen its high-density power electronics position for AI applications. Empower developed integrated voltage regulators (IVRs) and silicon-based capacitor technology that enable power conversion closer to the processor, shortening the power path and reducing losses. ADI's CEO noted that energy delivery has become the primary bottleneck for AI system scaling.

AI伺服器中電源路徑保護的核心器件是什么？ What is the core component for power path protection in AI servers?

以TI的TPS1685為代表，這是具有電源路徑保護的48V集成式熱插拔電子保險絲。它使設計人員能夠通過可擴展器件滿足高功率處理需求，同時簡化設計、縮小尺寸，是48V電源架構中保護CPU、GPU和AI加速器的關鍵器件。

The TI TPS1685 is representative: a 48V integrated hot-swap eFuse with power path protection. It enables designers to meet high-power handling requirements through scalable devices while simplifying design and reducing size. It is a key component for protecting CPUs, GPUs, and AI accelerators in 48V power architectures.

AI數據中心從12V轉向48V供電架構的原因是什么？ Why are AI data centers transitioning from 12V to 48V power architectures?

隨著AI工作負載激增，數據中心設計人員正在轉向48V電源架構，以提高效率和可擴展性，從而更好地支持CPU、GPU和AI硬件加速器等高功率組件。TI的48V可堆疊熱插拔電子保險絲正是為滿足>6kW處理需求而設計。

As AI workloads surge, data center designers are moving to 48V power architectures to improve efficiency and scalability, better supporting high-power components such as CPUs, GPUs, and AI hardware accelerators. TI's 48V stackable hot-swap eFuse is designed precisely to meet power handling requirements above 6 kW.

TI的1kW伺服器PSU參考設計采用了哪些GaN器件？ Which GaN devices are used in TI's 1 kW server PSU reference design?

TIDA-010062參考設計采用LMG341x GaN FET（帶集成驅動器）用于連續導通模式圖騰柱無橋PFC級，以及LMG3422 GaN FET用于半橋LLC隔離式DC/DC級。PFC級峰值效率>98.8%，LLC級峰值效率>98.3%，符合80 Plus Titanium標準。

The TIDA-010062 reference design uses LMG341x GaN FETs with integrated drivers for the continuous conduction mode totem-pole bridgeless PFC stage, and LMG3422 GaN FETs for the half-bridge LLC isolated DC/DC stage. The PFC stage achieves >98.8% peak efficiency and the LLC stage >98.3%, meeting 80 Plus Titanium standards.

該1kW參考設計的數字控制核心是什么？ What is the digital control core of this 1 kW reference design?

使用C2000 Piccolo微控制器來控制兩個功率級（PFC級和LLC級），實現數字控制的緊湊型設計，適用于伺服器電源單元（PSU）和通信電源整流器應用。

A C2000 Piccolo microcontroller controls both power stages (PFC and LLC), enabling a compact digitally controlled design suitable for server power supply units (PSUs) and telecom power rectifier applications.

Arm對Agentic AI時代CPU需求的核心判斷是什么？ What is Arm's core assessment of CPU demand in the Agentic AI era?

Arm CEO Rene Haas指出，在相同電力條件下，未來數據中心所需的CPU核心數可能增至當前的4倍以上。Agentic AI除了生成答案，還需持續執行任務、調用工具、管理工作流，帶來的調度、分發、協調負載正越來越多地由CPU承擔。

Arm CEO Rene Haas noted that under the same power constraints, future data centers may require more than four times the number of CPU cores compared with today. Beyond generating answers, Agentic AI must continuously execute tasks, invoke tools, and manage workflows, with the resulting scheduling, distribution, and coordination loads increasingly borne by CPUs.

Arm AGI CPU的核心競爭力是什么？ What is the core competitiveness of Arm's AGI CPU?

能效是核心。該產品每瓦性能約為同級x86系統的兩倍。在風冷下36kW功耗支持8160個核心和>180TB內存；液冷下200kW支持>4.5萬核心和>1PB內存。大規模導入Arm架構CPU可減少約10GW電力需求。

Energy efficiency is central. The product delivers approximately twice the performance per watt of comparable x86 systems. Under air cooling, 36 kW supports 8160 cores and >180 TB of memory; under liquid cooling, 200 kW supports >45,000 cores and >1 PB of memory. Large-scale adoption of Arm-based CPUs could reduce power demand by approximately 10 GW.

哪些云廠商已采用Arm AGI CPU？ Which cloud providers have adopted Arm's AGI CPU?

Oracle Cloud Infrastructure (OCI) 和字節跳動（ByteDance）已采用。此外，Google Axion、AWS Graviton、Nvidia Grace和Vera等數據中心CPU產品均基于Arm架構設計。

Oracle Cloud Infrastructure (OCI) and ByteDance have adopted it. In addition, data center CPU products including Google Axion, AWS Graviton, and NVIDIA Grace and Vera are all designed on Arm architecture.

博通2026財年AI半導體業務的業績表現如何？ How did Broadcom's AI semiconductor business perform in fiscal 2026?

博通當季AI半導體收入167億美元，同比增長221%，占總營收56%。定制芯片占AI半導體收入的73%。谷歌最新TPU和OpenAI的Jalape?o芯片已開始出貨，面向Meta的定制芯片本季度開始出貨。

Broadcom reported quarterly AI semiconductor revenue of $16.7 billion, up 221% year-over-year and representing 56% of total revenue. Custom chips accounted for 73% of AI semiconductor revenue. Google's latest TPU and OpenAI's Jalape?o chip have begun shipping, with custom chips for Meta starting shipments this quarter.

博通對AI半導體收入的未來預期是什么？ What is Broadcom's forward outlook for AI semiconductor revenue?

博通將2026財年AI半導體收入指引上調至580億美元（同比+186%），已鎖定供應支撐2027財年翻倍至1150億美元，2028財年有望再翻倍至2300億美元。Jalape?o在2027年預計實現約1.3GW部署。

Broadcom raised its fiscal 2026 AI semiconductor revenue guidance to $58 billion (up 186% year-over-year), has secured supply to support a doubling to $115 billion in fiscal 2027, and potentially another doubling to $230 billion in fiscal 2028. Jalape?o is expected to reach approximately 1.3 GW of deployment in 2027.

Google TPU在WSC（倉儲規模計算機）中的定位是什么？ What is the positioning of Google TPU in WSC (Warehouse-Scale Computer) environments?

TPU強調穩健的軟件棧和可編程性，XLA編譯器執行關鍵優化（如融合）。VCU（視頻編碼單元）在計算容量上實現突破，支持多輸出轉碼等新能力。AV1編碼相比VP9需要5-10倍計算資源，VCU設計空間提供了更廣泛的權衡選擇。

TPU emphasizes a robust software stack and programmability, with the XLA compiler performing key optimizations such as fusion. The VCU (Video Coding Unit) achieves breakthroughs in compute capacity, supporting new capabilities such as multi-output transcoding. AV1 encoding requires 5–10x the compute resources of VP9, and the VCU design space offers a broader range of trade-offs.

華為提出的“τ擴展”核心論點是什么？ What is the core argument of Huawei's "τ scaling"?

τ擴展的核心事實是：大型AI集群中超過80%的能源消耗于數據傳輸，超過70%的系統成本分配給了數據存儲。減少數據傳輸時間（芯片間、機架間、封裝內部）至少與減少計算時間同等重要。

The central fact of τ scaling is that in large AI clusters, more than 80% of energy consumption is attributable to data transmission, and more than 70% of system cost is allocated to data storage. Reducing data transmission time—chip-to-chip, rack-to-rack, and within-package—is at least as important as reducing compute time.

“統一總線”（Unified Bus）如何降低AI系統延遲？ How does the Unified Bus reduce AI system latency?

統一總線用單一協議取代了傳統多協議棧（PCIe→NVLink/專有→以太網/InfiniBand），實現完全對等的內存語義暴露。端到端遠程訪問延遲從TCP/IP級協議的幾十微秒降至約100納秒，系統τ降低約500倍。

The Unified Bus replaces traditional multi-protocol stacks (PCIe → NVLink/proprietary → Ethernet/InfiniBand) with a single protocol, enabling fully symmetric memory semantics exposure. End-to-end remote access latency drops from tens of microseconds at TCP/IP-level protocols to approximately 100 nanoseconds, reducing system τ by roughly 500x.

Hi-ONE近封裝光引擎解決了什么問題？ What problem does the Hi-ONE near-package optical engine solve?

當每芯片帶寬達到數Tb/s時，銅纜布線在物理上不可行（SerDes產能達上限、布線體積過大、散熱不足）。Hi-ONE每個模組提供8 Tb/s帶寬，將SerDes傳輸距離從約100厘米縮短至約5厘米，傳輸距離從不足1米擴展至100米。

When per-chip bandwidth reaches several Tb/s, copper cabling becomes physically infeasible due to SerDes capacity limits, wiring volume, and insufficient thermal dissipation. Hi-ONE provides 8 Tb/s per module, shortening SerDes transmission distance from approximately 100 cm to about 5 cm, while extending reach from less than 1 meter to 100 meters.

Google IPU架構如何分離伺服器控制平面與數據平面？ How does Google's IPU architecture separate the server control plane from the data plane?

IPU將伺服器控制平面（監控、虛擬化、容器生命周期、網絡存儲I/O）與客戶工作負載分離到不同核心。控制平面開銷可能爆發至超過50%的總計算容量。IPU包含PCIe交換機，硬件加速虛擬化功能（靈活物理到虛擬映射、實時遷移、租戶隔離）。

The IPU separates the server control plane (monitoring, virtualization, container lifecycle, network and storage I/O) from customer workloads onto different cores. Control plane overhead can spike to more than 50% of total compute capacity. The IPU includes a PCIe switch and hardware-accelerated virtualization features such as flexible physical-to-virtual mapping, live migration, and tenant isolation.

smartNIC在WSC網絡中承擔什么角色？ What role do smartNICs play in WSC networks?

smartNIC需要滿足高吞吐、低延遲、低尾延遲、流量整形、OS繞過、線速加密、可調試性等要求，同時保持低主機CPU占用。方案包括onload（主機CPU提供低延遲）和offload（NIC卡處理數據包和加密）。Google的IPU將控制平面與數據平面分離是代表性實現。

SmartNICs must satisfy requirements including high throughput, low latency, low tail latency, traffic shaping, OS bypass, line-rate encryption, and debuggability, while maintaining low host CPU utilization. Approaches include onload (host CPU provides low latency) and offload (the NIC handles packets and encryption). Google's IPU, which separates the control plane from the data plane, is a representative implementation.

為什么AI加速器必然走向3D折疊？ Why must AI accelerators inevitably move toward 3D folding?

幾何學決定了這一趨勢。在傳統2.5D封裝中，計算能力與N2（面積）成正比，但內存帶寬、互連和供電僅與N（周長）成正比。所有信號和電流必須沿芯片邊緣傳輸才能到達內部計算資源，這構成了根本性瓶頸。

Geometry dictates this trend. In conventional 2.5D packaging, compute capacity scales with N2 (area), but memory bandwidth, interconnect, and power delivery scale only with N (perimeter). All signals and current must travel along the chip edge to reach internal compute resources, constituting a fundamental bottleneck.

Nvidia RTX Spark平臺的核心特點是什么？ What are the core characteristics of the NVIDIA RTX Spark platform?

該PC算力平臺搭載MediaTek定制的Grace CPU（基于Arm架構）。Nvidia CEO黃仁勛表示，PC將從“人直接運行應用”轉向“代理執行任務的算力平臺”。借助NVFP4模型壓縮格式，未來PC可運行參數規模達1000億的AI模型。

This PC compute platform is powered by a MediaTek-customized Grace CPU based on Arm architecture. NVIDIA CEO Jensen Huang stated that PCs will shift from "humans directly running applications" to "compute platforms that execute tasks on behalf of agents." With the NVFP4 model compression format, future PCs will be able to run AI models with up to 100 billion parameters.

AI數據中心供電架構正在發生什么根本性變革？ What fundamental transformation is underway in AI data center power delivery architecture?

從傳統配電架構轉向高壓直流（HVDC），同時液冷散熱成為標配。AI的爆發使數據中心基礎設施全面轉向高效能液冷與HVDC供電架構，芯片端主被動元件創新與封裝優化成為支撐極致功率密度的底層關鍵。

A shift from traditional power distribution architectures to high-voltage direct current (HVDC), with liquid cooling becoming standard. The AI surge is driving data center infrastructure comprehensively toward high-efficiency liquid cooling and HVDC power architectures, with innovations in active and passive components at the chip level and packaging optimization serving as the underlying keys to supporting extreme power density.

TI 800VDC架構中“兩級轉換”的具體路徑是什么？ What is the specific "two-stage conversion" path in TI's 800 VDC architecture?

第一級：800V至6V隔離式母線轉換器（集成GaN，97.6%峰值效率，>2000W/in3）；第二級：6V至<1V多相降壓轉換器（高電流密度，雙相功率級設計）。僅需兩步即可從800V降至GPU核心電壓。

Stage one: an 800V-to-6V isolated bus converter with integrated GaN (97.6% peak efficiency, >2000 W/in3). Stage two: a 6V-to-sub-1V multiphase step-down converter with high current density and a dual-phase power stage design. Only two steps are required to bring 800V down to GPU core voltage.

Raysen Industry Hong Kong Limited

核心優勢

Core Strengths

主流芯片品牌

Industry-Leading Chips

TI 電源管理

TI Power Management

ADI 信號鏈

ADI Signal Chain

兩款 AI 模組

Two AI Modules

技術問答

Technical Q&A

應用場景

Applications

邊緣計算

Edge Computing

智能推理

Intelligent Inference

數據中心加速

Data Center Acceleration

關于我們

About Us

Company Profile

Core Business

R&D Capabilities

Industry Landscape

Vision

產品中心

Products

AI 伺服器模組

AI Server Modules

電源管理設計

Power Management Design

信號鏈設計

Signal Chain Design

工業研發與生產

Industrial R&D and Manufacturing

技術與研發

Technology & R&D

電源與功率級

Power & Power Stages

穩壓與信號調理

Regulation & Signal Conditioning

AI 伺服器模組

AI Server Modules

聯系我們

Contact Us